FPGA Acceleration based MEC Platform

1. FPGA-based Mobile Edge Computing(MEC) Framework
Many future IT scenarios require, such as smart factory, smart house, smart building and connected car, require ultra reliable low latency communication (URLLC) performance. Mobile Edge Computing (MEC) has emerged as one of the solutions, which is a network architecture concept that enables cloud computing capabilities and an IT service environment at the edge of the cellular network. The MEC reduces network time and provides fast response time by running an application service closer to the cellular customer.

Figure 1. MEC accelerated with FPGA

To more reduce the service time of MEC application, we build MEC server with hardware accelerators, especially FPGA that has low power characteristic. However, the hardware characteristics of the FPGA make several obstructions to the MEC service deployment. As a solution, we construct the MEC-FPGA framework, which makes it easier for MEC application service providers to deploy services using the FPGA accelerator.

1-1. MEC Platform Architecture with FPGA
  • We put MEC Platform between C-RAN and vEPC
  • One of the key features of the MEC Platform is virtualization: both on network and resource
  • To support the virtualization, we use Docker and Kubernetes in implementing the MEC Platform.
  • Especially, we have developed a Pass through engine that supports the use of FPGAs in Containers, and configure a platform that allows Kubernetes to manage them.

Figure 3. FPGA enabled MEC Platform architecture

1-2. FPGA Virtualization
  • FPGA virtualization with four logic-locked FPGA regions
  • Support Dynamic Partial Reconfiguration in each vFPGA region
  • Custom MMD library and driver which are compatible with Intel OpenCL SDK

Figure 4. FPGA Virtualization via partial reconfiguration

1-3. HW scheduling
  • A reconfiguration time overhead aware scheduling mechanism lay between MMD layer and driver layer
  • Select a proper vFPGA base on service characteristics and available resources

Figure 5. FPGA Hardware scheduler


2. Verifying the feasibility of using FPGA as accelerator in MEC

Figure 6. SIFT object detection

To verify the feasibility of using an FPGA as an accelerator, we implemented an image processing (among which we selected the SIFT algorithm) that can be used for MEC applications using an FPGA.

Figure 7. Algorithm for SIFT object detection

We assumed a scenario using the MEC for image processing in the Smart Factory, and obtained the gain at that speed as a result of processing the SIFT in the FPGA. Based on the scenario we build a PoC for the MEC with accelerators

Figure 8. CV Application on FPGA based Accelerator

  • heterogeneous many-core hardware system for UHPC


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